Contents :- Laser Voltage Probe (LVP): A Novel Optical Probing Technology for Flip-Chip Packaged Microprocessors - Scanning Electron Acoustic Microscopy: A Novel Tool for Failure Analysis & Microcharacterisation - Application of Single Contact Optical Beam Induced Currents (SCOBIC) for Backside Failure Analysis - Measurement of Interfacial Adhesion and Its Degradation in Multi-Layer Packages, Devices, And Blanket Films Using the Laser Spallation Technique - New FIB-Supported Approach for Wirebond Characterization - Failure Analysis of Flip Chip Bumps after Thermal Stressing - X-Ray Tomography for Electronic Packages - Data Analysis Tools and Methodologies for Quick Yield Learning in a High Volume Manufacturing Environment - Failure Analysis of Killer Defects and Yield Enhancement of Flat ROM Devices in Wafer Fabrication - Embedded Memory Analysis for Standard Cell ASIC Yield Enhancement - Yield Enhancement Study: Process Variation and Design Margins Leading to Timing Issues in RAM - In-line Defect to Bitmap Signature Correlation: A Shortcut to Physical FA Results - Analysis of Leakage Failures in Flash Memory Devices and Root Cause Identification - Passive Voltage Contrast Application on Analysis of Gate Oxide Failure in 0.25 μm Technology - Forensic Microscopy in the Failure Analysis Laboratory - Failure Analysis Process Flow and Common Failure Mechanisms in Flip-Chip Packaged Devices - A Study on the Yield Loss Due to Al (Cu) Interconnections with Spacing Failure - Near IR Absorption in Heavily Doped Silicon–An Empirical Approach - Embedded SRAM Bitmapping and Failure Analysis for Manufacturing Yield Improvement - LSI Process Diagnosis for Device Users - Application of KOH Electrochemical Etch and Passive Voltage Contrast Techniques to Identify Leaky Gate in Deep Submicron CMOS - UV Reflectance Spectroscopy of the Copper/Copper Oxide System for Assessment of Solderability - Antireflection Coatings for Semiconductor Failure Analysis - Comparative Study of Sample Preparation Techniques for Backside Analysis - A Comparison of Backside Emission Microscopy Systems - Failure Analysis from the Back Side of a Die - ESD Effects on Electromigration Performance of Aluminum Metallization System - Evaluation of On-Chip ESD Supply Clamp Robustness by In-situ Floating Power Bus Monitoring - Transmission Line Pulse Testing of the ESD Protection Structures of ICs.-A Failure Analysts Perspective - Failure Analysis of CDM ESD Damage in a GaAs RFIC - A Focused Ion Beam Technique to Electrically Contact the Deep Trench Capacitor of a Single Active Memory Cell in the Sub 0.25 μm Technology Regime - The Use of TMAH to Etch Silicon and Expose Metal Bridging Failures - Selective Au Etching in Au/Al Bonds in Current IC Technology - A Novel Method to Analyze the Deep Trench Capacitors in DRAM - Identification and Analysis of Parasitic Depletion Mode Leakage in a Memory Select Transistor - Thermal Fatigue Induced Voiding in LDMOS Transistors Submitted to Multiple Energy Discharges - Humidity-Bias Driven Shorts in Multilayer Circuits: A Case Study in Failure Analysis - Passivation Cracks in a Four-Level Metal Low-k Dielectric Backend Process - Electronic Package Failure Analysis Using TDR - Time Domain Reflectometry as a Device Packaging Level Failure Analysis and Failure Localization Tool - Contrast Inversions in Scanning Acoustic Microscopy (C-SAM) of Glue Die Attach - Application of Scanning Acoustic Microscopy tom Electric and Electronic Parts - Combining FIB Sequential Cross-Sectioning With TEM for Small Defect Analysis in SRAM Array - Failure Analysis of Tungsten Stud Defects from the CMP Process - Integrated Circuit SNR Improvement using Dielectric Altering Compound, Laser Trim, and FIB system - Characterization and Isolation Techniques in Silicon on Insulator Technology Microprocessor Designs - Failure Analysis of Stacked-Chip Scale Package - Reducing Top-of-Die Plastic Delamination by Assuring Pre-Mold Cleanliness of Die Surfaces - SMT Ceramic Capacitor Failure Mechanisms, Isolation Tools, Techniques and Analysis Methods - Case Studies of Brittle Interfacial Failures in Area Array Solder Interconnects - Failure Analysis and Elimination of Galvanic Corrosion on Bondpads During Wafer Sawing - High Temperature Solder (Au/Sn) Failures from Nickel Plating Impurities - Semiconductor Wear Out at Nuclear Power Plants - UTC Clinic Hospital Network: Description of International Network of Failure Analysis Labs and Case Studies - Wafer Conserving Full Range Construction Analysis for IC Fabrication and Process Development Based on- Index