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"This book provides readers with an overview of the architectures, programming frameworks, and hardware accelerators for typical cloud computing applications in data centers. The authors present the most recent and promising solutions, using hardware accelerators to provide high throughput, reduced latency and higher energy efficiency compared to current servers based on commodity processors. Readers will benefit from state-of-the-art information regarding application requirements in contemporary data centers, computational complexity of typical tasks in cloud computing, and a programming framework for the efficient utilization of the hardware accelerators."

"This book gives a comprehensive and systematic review of secure compressive sensing (CS) for applications in various fields such as image processing, pattern recognition, Internet of things (IoT), and cloud computing. It will help readers grasp the knowledge of secure CS and its applications, and stimulate more readers to work on the research and development of secure CS. It discusses how CS becomes a cryptosystem, followed by the corresponding designs and analyses. The application of CS in multimedia data encryption is presented, in which the general design framework is given together with several particular frameworks including parallel CS, involvement of image processing techniques, and double protection mechanism. It also describes the applications of CS in cloud computing security and IoT security, i.e., privacy-preserving reconstruction in cloud computing and secure low-cost sampling in IoT, respectively."

"This book suggests and describes a number of fast parallel circuits for data/vector processing using FPGA-based hardware accelerators. Three primary areas are covered: searching, sorting, and counting in combinational and iterative networks. These include the application of traditional structures that rely on comparators/swappers as well as alternative networks with a variety of core elements such as adders, logical gates, and look-up tables. The iterative technique discussed in the book enables the sequential reuse of relatively large combinational blocks that execute many parallel operations with small propagation delays. For each type of network discussed, the main focus is on the step-by-step development of the architectures proposed from initial concepts to synthesizable hardware description language specifications. Each type of network is taken through several stages, including modeling the desired functionality in software, the retrieval and automatic conversion of key functions, leading to specifications for optimized hardware modules. The resulting specifications are then synthesized, implemented, and tested in FPGAs using commercial design environments and prototyping boards. The methods proposed can be used in a range of data processing applications, including traditional sorting, the extraction of maximum and minimum subsets from large data sets, communication-time data processing, finding frequently occurring items in a set, and Hamming weight/distance counters/comparators. The book is intended to be a valuable support material for university and industrial engineering courses that involve FPGA-based circuit and system design."