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"Contents :- Laser Voltage Probe (LVP): A Novel Optical Probing Technology for Flip-Chip Packaged Microprocessors - Scanning Electron Acoustic Microscopy: A Novel Tool for Failure Analysis & Microcharacterisation - Application of Single Contact Optical Beam Induced Currents (SCOBIC) for Backside Failure Analysis - Measurement of Interfacial Adhesion and Its Degradation in Multi-Layer Packages, Devices, And Blanket Films Using the Laser Spallation Technique - New FIB-Supported Approach for Wirebond Characterization - Failure Analysis of Flip Chip Bumps after Thermal Stressing - X-Ray Tomography for Electronic Packages - Data Analysis Tools and Methodologies for Quick Yield Learning in a High Volume Manufacturing Environment - Failure Analysis of Killer Defects and Yield Enhancement of Flat ROM Devices in Wafer Fabrication - Embedded Memory Analysis for Standard Cell ASIC Yield Enhancement - Yield Enhancement Study: Process Variation and Design Margins Leading to Timing Issues in RAM - In-line Defect to Bitmap Signature Correlation: A Shortcut to Physical FA Results - Analysis of Leakage Failures in Flash Memory Devices and Root Cause Identification - Passive Voltage Contrast Application on Analysis of Gate Oxide Failure in 0.25 μm Technology - Forensic Microscopy in the Failure Analysis Laboratory - Failure Analysis Process Flow and Common Failure Mechanisms in Flip-Chip Packaged Devices - A Study on the Yield Loss Due to Al (Cu) Interconnections with Spacing Failure - Near IR Absorption in Heavily Doped Silicon–An Empirical Approach - Embedded SRAM Bitmapping and Failure Analysis for Manufacturing Yield Improvement - LSI Process Diagnosis for Device Users - Application of KOH Electrochemical Etch and Passive Voltage Contrast Techniques to Identify Leaky Gate in Deep Submicron CMOS - UV Reflectance Spectroscopy of the Copper/Copper Oxide System for Assessment of Solderability - Antireflection Coatings for Semiconductor Failure Analysis - Comparative Study of Sample Preparation Techniques for Backside Analysis - A Comparison of Backside Emission Microscopy Systems - Failure Analysis from the Back Side of a Die - ESD Effects on Electromigration Performance of Aluminum Metallization System - Evaluation of On-Chip ESD Supply Clamp Robustness by In-situ Floating Power Bus Monitoring - Transmission Line Pulse Testing of the ESD Protection Structures of ICs.-A Failure Analysts Perspective - Failure Analysis of CDM ESD Damage in a GaAs RFIC - A Focused Ion Beam Technique to Electrically Contact the Deep Trench Capacitor of a Single Active Memory Cell in the Sub 0.25 μm Technology Regime - The Use of TMAH to Etch Silicon and Expose Metal Bridging Failures - Selective Au Etching in Au/Al Bonds in Current IC Technology - A Novel Method to Analyze the Deep Trench Capacitors in DRAM - Identification and Analysis of Parasitic Depletion Mode Leakage in a Memory Select Transistor - Thermal Fatigue Induced Voiding in LDMOS Transistors Submitted to Multiple Energy Discharges - Humidity-Bias Driven Shorts in Multilayer Circuits: A Case Study in Failure Analysis - Passivation Cracks in a Four-Level Metal Low-k Dielectric Backend Process - Electronic Package Failure Analysis Using TDR - Time Domain Reflectometry as a Device Packaging Level Failure Analysis and Failure Localization Tool - Contrast Inversions in Scanning Acoustic Microscopy (C-SAM) of Glue Die Attach - Application of Scanning Acoustic Microscopy tom Electric and Electronic Parts - Combining FIB Sequential Cross-Sectioning With TEM for Small Defect Analysis in SRAM Array - Failure Analysis of Tungsten Stud Defects from the CMP Process - Integrated Circuit SNR Improvement using Dielectric Altering Compound, Laser Trim, and FIB system - Characterization and Isolation Techniques in Silicon on Insulator Technology Microprocessor Designs - Failure Analysis of Stacked-Chip Scale Package - Reducing Top-of-Die Plastic Delamination by Assuring Pre-Mold Cleanliness of Die Surfaces - SMT Ceramic Capacitor Failure Mechanisms, Isolation Tools, Techniques and Analysis Methods - Case Studies of Brittle Interfacial Failures in Area Array Solder Interconnects - Failure Analysis and Elimination of Galvanic Corrosion on Bondpads During Wafer Sawing - High Temperature Solder (Au/Sn) Failures from Nickel Plating Impurities - Semiconductor Wear Out at Nuclear Power Plants - UTC Clinic Hospital Network: Description of International Network of Failure Analysis Labs and Case Studies - Wafer Conserving Full Range Construction Analysis for IC Fabrication and Process Development Based on- Index"

"Contents - IPFA 2000 Best Paper Award Winner - Application of Focused Ion Beam System as a Defect Localization and Root Cause Analysis Tool - Session 1: Advanced Techniques 1 - X-Ray Tomography of Integrated Circuit Interconnects: Past and Future - X-ray Nanotomog Raphy (XRMT) Tool for Non-Destructive High-Resolution Imaging of ICs - Single Point PICA Probing with an Avalanche Photo-Diode - Session 2: Advanced Techniques 2 - Comparison of Laser and Emission Based Optical Probe Techniques - Resistive Interconnection Localization - Optical Waveform Probing–Strategies for Non-Flipchip Devices and Other Applications - Advanced LIVA/TIVA Techniques - Session 3: Packaging - Super-conducting Quantum Interference Device Technique: 3-D Localization of a Short Within a Flip Chip Assembly - Integration of SQUID Microscopy into FA Flow - Evaluation of alternative Preparation Methods for Failure Analysis at modern Chip-and Package Technologies - TDR Analysis of Advanced Microprocessors - Signal Trace and Power Plane Shorts Fault Isolation Using TDR - Session 4: Poster Session - Backside Etch: A New FA Technique for Gate Oxide Pinhole and Si Defect Identification for Power IC Devices - Fabrication Of Inexpensive Decapsulation Fixtures for Small or Unique Plastic Packages - Failure Analysis of Plasma-Induced Submicron CMOS IC Yield Loss by Backside Photoemission Microscopy - Failure Types & Analysis In Cu Process Development of Design-Rule 0.18 μm CPU - TEM Examination of a Specified Site Identified by X-SEM in Microelectronics Failure Analysis - Design Debug and Design Fix Verification in a Failure Analysis Lab for a RF/IF Circuit for Cellular Applications With High Battery Save and Electrostatic Discharge Leakage: A Case Study - Self Aligned Contact Wordline-Bitline Shorts in Memory ICs–a Comparative Study of a Failure Mode, Its Root Causes, And Simple, But Highly Effective Analysis Techniques - A Spatial Filtering Localisation Tool for Failure Analysis of Periodic Circuits - New Manifestation of Electrical Overstress in Advanced Device Technologies - Session 5: Backside 1 - Implementing Thermal Laser Stimulation in a Failure Analysis Laboratory - Calibration Technique for MCT FPA used for Backside Emission Microsopy - Liquid Immersion Objective for High-Resolution Optical Probing of Advanced Microprocessors - New Signal Detection Methods for Thermal Beam Induced Phenomenon - CNC Milling and Polishing Techniques for Backside Sample Preparation - Session 6: SPM - Characterization of MOS Devices by Scanning Thermal Microscopy (SThM) - Contactless Failure Analysis of Integrated Circuits Via Current Contrast Imaging with Magnetic Force Microscopy - Multiple Probe Deep Sub-Micron Electrical Measurements Using Leading Edge Micro-Machined Scanning Probes - Electrical Characterization of Circuits with Low K Dielectric Films and Copper Interconnects - Session 7: Backside 2 - Emission Microscopy and Thermal Laser Stimulation for Backside Failure Localization - CMOS Front-End Investigation over Large Areas by Deprocessing from the Back Side - New Techniques for the Identification of Defects in Multi-Layer Flip-Chip Packages - Session 8: Case Histories 1 - Board Level Failure Analysis of Chip Scale Packages - IC Failure by Electrical Overstress (EOS) - The Search for the Elusive EOS Monster - Session 9: FIB - Effect of Ga Staining due to FIB Editing on IR Imaging of Flip Chips - Water Vapor Enhancement for Elemental Analysis Using Focused Ion Beam Secondary Ion Mass Spectrometry (FIB-SIMS) - Various Focused Ion Beam Microsurgery Techniques in Dealing with Copper Metalization in ICs - Reliability of Bipolar and MOS Circuits After FIB Modification - Mass Production Cross-Section Tem Samples by Focus Ion Beam Masking and Reactive Ion Etching - Session 10: Case Histories 2 - A Successful Failure Analysis Using Front and Backside Fault Localization Techniques on a Deep Sub-Micron CMOS Device - Use of STEM in Nanometer Level Defect Analysis of SRAM Devices - A New Deprocessing Technique By Selective Wet-Etch Of Passivation And Inter Metal Dielectric Layers For Submicron Devices - SRAM Failure Analysis Flow - Physical Failure Analysis on Vertical Dielectric Films - Session 11: MEMS - Design for Reliability of MEMS/MOEMS for Lightwave Telecommunications - Mechanical Characterization of Materials Used in MEMS - Optical Imaging of High-Frequency Resonances and Semi-Static Deformations in Micro-Elec"