[ABSTRAK Perancangan VLSI dengan hybrid VHDL merupakan metode desain untukmenghasilkan Sistem On Chip yang berbasis FPGA Xilinx Spartan 3. Sistem yangdi desain adalah arsitektur CPU yang terdapat di Ocean Bottom Unit (OBU)Tsunami Early Warning System. Proses desain di implementasikan pada FPGAboard Xilinx Spartan 3.Perancangan VLSI CPU OBU dengan metode hybrid VHDL di lakukandengan urutan proses desain yaitu membuat kode VHDL untuk menyimpan datapengukuran dan mengolah dengan algoritma mofjeld, Mengubah kode VHDLmenjadi RTL, Mengubah RTL menjadi schematic dan kode verilog, Mengubahverilog menjadi CMOS layout, Menggunakan kode VHDL sebagai configuredevice pada XC3S200, genetrate PROM file pada XCF02S.Hasil rancangan adalah VLSI 0,25 μm pada CPU OBU dengan jumlahgerbang logika yang digunakan sebanyak 699 buah dan 347 buah flipflop.Sedangkan dalam teknologi VLSI kapasitas adalah 10k -1M. Dengan metodehybrid VHDL jumlah gate pada desain CPU OBU masih dapat ditingkatkandengan cara meningkatkan memori simpan sebanyak mungkin.;VLSI design with a hybrid VHDL is a design methods to produce a SystemOn Chip based on CMOS layout. The designed system is CPU architecturelocated on Ocean Bottom Unit Tsunami Early Warning System. The designprocess implemented on Xilinx Spartan 3 FPGA board.Design of VLSI OBU CPU with a hybrid VHDL method is done by orderof the design process is to make VHDL code for storing and processing themeasurement data with the algorithm mofjeld, Changing the VHDL code intoRTL, Changing RTL into schematic and verilog file, Changing verilog code intoCMOS layout, Using the VHDL code as configure devices on the XC3S200,generating PROM files on XCF02S Xilinx Spartan.The design results is VLSI 0,25 μm in CPU OBU with 699 logic gates and347 flip-flops. While in VLSI technology the capacity is 10k-1M. With a hybridmethod the gate of CPU OBU can be increased by increasing the memory asmuch as possible.;VLSI design with a hybrid VHDL is a design methods to produce a SystemOn Chip based on CMOS layout. The designed system is CPU architecturelocated on Ocean Bottom Unit Tsunami Early Warning System. The designprocess implemented on Xilinx Spartan 3 FPGA board.Design of VLSI OBU CPU with a hybrid VHDL method is done by orderof the design process is to make VHDL code for storing and processing themeasurement data with the algorithm mofjeld, Changing the VHDL code intoRTL, Changing RTL into schematic and verilog file, Changing verilog code intoCMOS layout, Using the VHDL code as configure devices on the XC3S200,generating PROM files on XCF02S Xilinx Spartan.The design results is VLSI 0,25 μm in CPU OBU with 699 logic gates and347 flip-flops. While in VLSI technology the capacity is 10k-1M. With a hybridmethod the gate of CPU OBU can be increased by increasing the memory asmuch as possible., VLSI design with a hybrid VHDL is a design methods to produce a SystemOn Chip based on CMOS layout. The designed system is CPU architecturelocated on Ocean Bottom Unit Tsunami Early Warning System. The designprocess implemented on Xilinx Spartan 3 FPGA board.Design of VLSI OBU CPU with a hybrid VHDL method is done by orderof the design process is to make VHDL code for storing and processing themeasurement data with the algorithm mofjeld, Changing the VHDL code intoRTL, Changing RTL into schematic and verilog file, Changing verilog code intoCMOS layout, Using the VHDL code as configure devices on the XC3S200,generating PROM files on XCF02S Xilinx Spartan.The design results is VLSI 0,25 μm in CPU OBU with 699 logic gates and347 flip-flops. While in VLSI technology the capacity is 10k-1M. With a hybridmethod the gate of CPU OBU can be increased by increasing the memory asmuch as possible.] |