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FinFET (Fin Field-EffectTransistor) technology has recently seen a major increase in adoptionfor use in integrated circuits because of its high immunity to short channeleffects and its further ability to scaledown. Previously, a major research contribution was made to reduce the leakage current in theconventional bulk devices. So many different alternatives like bulk isolation and oxide isolation are all having some pros andcons. Here in this paper, we present a novel pile gate FinFET structure toreduce the leakage current, as compared with Bulk FinFET without using any pstop implant orisolation oxide as in theSilicon-on-Insulator (SOI). The major advantage of this type ofstructure is that there is no need of high substrate doping, a 100% reduction in therandom dopant fluctuation (RDF) and an increase in the ION/IOFFvalue. It can be very useful to improve the drain-induced barrier lowering (DIBL) at smallertechnological nodes. All the work is supported by 3D TCAD simulations, using Cogenda TCAD. |
