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Learning from VLSI design experience

Weng Fook Lee (Springer Nature, 2019)

 Abstrak

This book shares with readers practical design knowledge gained from the authors 24 years of IC design experience. The author addresses issues and challenges faced commonly by IC designers, along with solutions and workarounds. Guidelines are described for tackling issues such as clock domain crossing, using lockup latch to cross clock domains during scan shift, implementation of scan chains across power domain, optimization methods to improve timing, how standard cell libraries can aid in synthesis optimization, BKM (best known method) for RTL coding, test compression, memory BIST, usage of signed Verilog for design requiring +ve and -ve calculations, state machine, code coverage and much more. Numerous figures and examples are provided to aid the reader in understanding the issues and their workarounds.
Addresses practical design issues and their workarounds;
Discusses issues such as CDC, crossing clock domain in shift, scan chains across power domain, timing optimization, standard cell library influence on synthesis, DFT, code coverage, state machine;
Provides readers with an RTL coding guideline, based on real experience.

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 Metadata

No. Panggil : e20509156
Entri utama-Nama orang :
Subjek :
Penerbitan : Switzerland: Springer Nature, 2019
Sumber Pengatalogan: LibUI eng rda
Tipe Konten: text
Tipe Media: computer
Tipe Pembawa: online resource
Deskripsi Fisik: xxix, 214 pages : illustration
Tautan: https://doi.org/10.1007/978-3-030-03238-8
Lembaga Pemilik:
Lokasi:
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No. Panggil No. Barkod Ketersediaan
e20509156 02-20-077644827 TERSEDIA
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