Ditemukan 1 dokumen yang sesuai dengan query
Taraate, Vaibbhav, author
This book describes RTL design using Verilog, synthesis and timing closure for System On Chip (SOC) design blocks. It covers the complex RTL design scenarios and challenges for SOC designs and provides practical information on performance improvements in SOC, as well as Application Specific Integrated Circuit (ASIC) designs. Prototyping using...
Singapore: Springer Nature , 2019
e20505551
eBooks Universitas Indonesia Library
