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"The subject of this book is the analysis and design of digital devices that implement computer arithmetic. The book's presentation of high-level detail, descriptions, formalisms and design principles means that it can support many research activities in this field, with an emphasis on bridging the gap between algorithm optimization and hardware implementation. The author provides a unified view linking the domains of digital design and arithmetic algorithms, based on original formalisms and hardware description languages.A feature of the book is the large number of examples and the implementation details provided."

"This is the first book to focus on the problem of ensuring the correctness of floating-point hardware designs through mathematical methods. Formal Verification of Floating-Point Hardware Design advances a verification methodology based on a unified theory of register-transfer logic and floating-point arithmetic that has been developed and applied to the formal verification of commercial floating-point units over the course of more than two decades, during which the author was employed by several major microprocessor design companies. The book consists of five parts, the first two of which present a rigorous exposition of the general theory based on the first principles of arithmetic. Part I covers bit vectors and the bit manipulation primitives, integer and fixed-point encodings, and bit-wise logical operations. Part II addresses the properties of floating-point numbers, the formats in which they are encoded as bit vectors, and the various modes of floating-point rounding. In Part III, the theory is extended to the analysis of several algorithms and optimization techniques that are commonly used in commercial implementations of elementary arithmetic operations. As a basis for the formal verification of such implementations, Part IV contains high-level specifications of correctness of the basic arithmetic instructions of several major industry-standard floating-point architectures, including all details pertaining to the handling of exceptional conditions. Part V illustrates the methodology, applying the preceding theory to the comprehensive verification of a state-of-the-art commercial floating-point unit. All of these results have been formalized in the logic of the ACL2 theorem prover and mechanically checked to ensure their correctness. They are presented here, however, in simple conventional mathematical notation. The book presupposes no familiarity with ACL2, logic design, or any mathematics beyond basic high school algebra. It will be of interest to verification engineers as well as arithmetic circuit designers who appreciate the value of a rigorous approach to their art, and is suitable as a graduate text in computer arithmetic."

"Pada pengembangan sistem, dibutuhkan sebuah mekanisme untuk menjamin bahwa sistem tersebut berjalan dengan benar tanpa error atau rsquo;bug rsquo;. Sejauh ini, hal yang biasa dilakukan adalah dengan testing, tetapi hal ini sulit dilakukan untuk mencakup semua kemungkinan. Untuk sistem yang membutuhkan tingkat correctness yang tinggi, seperti misalnya pada hardware , perlu mekanisme yang dapat menjamin kebenaran program untuk semua kemungkinan input. Ada solusi lain yang dapat menjamin kebenaran program untuk semua kemungkinan input, yaitu dengan verifikasi formal. Verifikasi formal dilakukan dengan pemodelan matematika. Salah satu sistem yang membutuhkan tingkat correctness yang tinggi adalah sistem bilangan floating-point. Hal ini terkait dengan pengalaman yang dialami Intel pada tahun 1994. Salah satu bahasa standar dalam membangun sebuah sistem digital atau hardware adalah VHDL. Ada beberapa tools yang bisa dilakukan untuk verifikasi formal, salah satunya adalah HOL theorem prover. Penelitian ini melakukan formalisasi operasi aritmatika VHDL dan konstruksi terkait yang dilakukan dengan menggunakan HOL Theorem Prover. Hasilnya adalah sebuah framework yang berisi formalisasi beberapa algoritma aritmatika dasar VHDL dan konstruksi terkaitnya. Framework ini kemudian dapat digunakan untuk memverifikasi modul VHDL yang memanfaatkan aritmatika VHDL dan konstruksi terkaitnya.

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In system development, a mechanism is needed to ensure that the system runs correctly without error or rsquo bug rsquo . So far, testing is a common solution, but it rsquo s hard to cover all error possibilities. For systems that require a high level of correctness, such as hardware systems, there is a need for a mechanism that can ensure the correctness of the program for all possible inputs. There is another solution to do the task, i.e. by formal verification. Formal verification is done by mathematical modeling. One system that requires a high level of correctness is the floating point number system. This is related to the experience of Intel in 1994.

One of the standard languages in developing a digital system or a hardware is VHDL. There are several tools that can be used for formal verification, one of which is HOL Theorem Prover. This research conducts a formalization of VHDL arithmetic operation and the related constructions done by using HOL Theorem Prover. The result is a framework which contains the formalization of some basic VHDL arithmetic algorithms and the related constructions. This framework can then be used to verify VHDL modules that utilize the VHDL arithmetic and the related constructs."