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"This book brings together a selection of the best papers from the thirteenth edition of the Forum on specification and Design Languages Conference (FDL), which was held in Southampton, UK in September 2010. FDL is a well established international forum devoted to dissemination of research results, practical experiences and new ideas in the application of specification, design and verification languages to the design, modelling and verification of integrated circuits, complex hardware/software embedded systems, and mixed-technology systems."

"This book brings together a selection of the best papers from the twentiethedition of the Forum on specification and Design Languages Conference (FDL), which took place on September 18-20, 2017, in Verona, Italy. FDL is a well-established international forum devoted to dissemination of research results, practical experiences and new ideas in the application of specification, design and verification languages to the design, modeling and verification of integrated circuits, complex hardware/software embedded systems, and mixed-technology systems.Covers modeling and verification methodologies targeting digital and analog systems;Addresses firmware development and validation;Targets both functional and non-functional properties;Includes descriptions of methods for reliable system design."

"This volume contains a selection of contributions that were presented at the Modeling and Optimization : Theory and Applications Conference (MOPTA) held at Lehigh University in Bethlehem, Pennsylvania, USA on August 18-20, 2010. The conference brought together a diverse group of researchers and practitioners, working on both theoretical and practical aspects of continuous or discrete optimization. Topics presented included algorithms for solving convex, network, mixed-integer, nonlinear, and global optimization problems, and addressed the application of optimization techniques in finance, logistics, health, and other important fields. "

"H. Gregor Molter develops a hardware / software co-design flow based on the Discrete Event System Specification model of computation. He advocates that such a system level design flow should exploit a timed model of computation to allow a broad application field. The presented design flow will transform timed DEVS models to both synthesizable VHDL source code and embeddable C++ source code."