Hasil Pencarian

Ditemukan 13 dokumen yang sesuai dengan query

Bhasker, J.

A VHDL primer / J. Bhasker

New Jersey: Prentice-Hall, 1992

621.392 BHA v

Buku Teks Universitas Indonesia Library

Petrus Mursanto, author

Perancangan Library Pemroses Aritmetis (Arithmetic Unit) dalam VHDL

ABSTRAK
Telah banyak usaha yang dilakukan untuk menyederhanakan proses implementasi suatu algoritma ke dalam rangkaian digital, yang sering disebut sebagai Application Specific Integrated Circuit (ASIC). Selain ringkas dan menjadi makin modular, rangkaian digital juga menjanjikan proses yang lebih cepat dibandingkan dengan eksekusi algoritma yang dijalankan oleh general purpose processor (GPP). Sebuah...

Fakultas Ilmu Komputer Universitas Indonesia, 2002

LP-pdf

UI - Laporan Penelitian Universitas Indonesia Library

LaMeres, Brock J., author

Introduction to logic circuits & logic design with VHDL

This textbook introduces readers to the fundamental hardware used in modern computers. The only pre-requisite is algebra, so it can be taken by college freshman or sophomore students or even used in Advanced Placement courses in high school. This book presents both the classical approach to digital system...

Switzerland: Springer Nature, 2019

e20509101

eBooks Universitas Indonesia Library

Sibarani, Evita Marlinang, author

Formalisasi dan verifikasi protokol komunikasi

Depok: Fakultas Ilmu Komputer Universitas Indonesia, 1997

S26978

UI - Skripsi Membership Universitas Indonesia Library

Computer hardware description languages and their applications : proceedings of the IFIP TC-10 Fifth International Conference on Computer Hardware Description Languages and Their Applications / editor, M. Breuer ; R. Hartenstein

Amsterdam: North Holland, 1981

621.391 COM

Buku Teks Universitas Indonesia Library

Ciletti, Michael D., author

Advanced digital design with the Verilog HDL

Boston : Prentice-Hall, 2011

621.395 CIL a

Buku Teks Universitas Indonesia Library

Spear, Chris, author

Systemverilog for verification: a guide to learning the testbench language features

Systemverilog for verification : a guide to learning the testbench language features teaches all verification features of the SystemVerilog language, providing hundreds of examples to clearly explain the concepts and basic fundamentals. In the third edition, authors Chris Spear and Greg Tumbush start with how to verify a design, and...

New York: [, Springer], 2012

e20418474

eBooks Universitas Indonesia Library

LaMeres, Brock J., author

Introduction to logic circuits & logic design with verilog

This textbook for courses in Digital Systems Design introduces students to the fundamental hardware used in modern computers. Coverage includes both the classical approach to digital system design (i.e., pen and paper) in addition to the modern hardware description language (HDL) design approach (computer-based). Using this textbook enables readers to...

Switzerland: Springer Nature, 2019

e20509097

eBooks Universitas Indonesia Library

Riyanto, examiner

Perancangan VLSI 0.25 μm dengan desain hybrid VHDL berbasis FPGA Xilinx Spartan 3 untuk CPU ocean bottom unit Tsunami Early Warning System = VLSI design 0.25 μm of a hybrid design with VHDL Xilinx Spartan 3 FPGA-based for ocean bottom unit CPU Tsunami Early Warning System

Perancangan VLSI dengan hybrid VHDL merupakan metode desain untuk menghasilkan Sistem On Chip yang berbasis FPGA Xilinx Spartan 3. Sistem yang di desain adalah arsitektur CPU yang terdapat di Ocean Bottom Unit (OBU) Tsunami Early Warning System. Proses desain di implementasikan pada FPGA board Xilinx Spartan 3. Perancangan VLSI CPU...

Depok: Fakultas Teknik Universitas Indonesia, 2012

T40836

UI - Tesis Open Universitas Indonesia Library

Elliott, John P., author

Understanding behavioral synthesis : a practical guide to high-level design

Boston: Kluwer Academic, 1999

621.381 5 ELL u

Buku Teks Universitas Indonesia Library

<< 1 2 >>

:: Hasil Pencarian :: Simpan CSV :: Kembali

Hasil Pencarian